This invention is in the field of nonvolatile semiconductor memory. Embodiments of this invention are more specifically directed to the programming of memory cells in an electrically erasable non-volatile memory.
Non-volatile solid-state read/write memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. A common technology for realizing non-volatile solid-state memory devices involves the trapping of charge at or near the gate element of a metal-oxide-semiconductor (MOS) transistor in the programmable memory cell. For example, electrically erasable programmable “read-only” memory (EEPROM) devices utilize “floating-gate” transistors to store the data state. According to this conventional technology, the memory cell transistor is “programmed” by biasing it so that electrons tunnel through a thin dielectric film onto an electrically isolated transistor gate element. Depending on the construction of the transistor, the tunneling mechanism may be Fowler-Nordheim tunneling or channel “hot” carrier injection. Another type of charge-trapping programmable memory cell involves the trapping of charge within the gate dielectric layer underlying the transistor gate element, or in some cases at the physical interface of the gate dielectric with silicon. In either case, trapped electrons at the gate region raise the apparent threshold voltage of the memory cell transistor (for n-channel devices), as compared with the threshold voltage with no electrons trapped at the gate. The stored state can be read by sensing the presence or absence of source-drain conduction under bias.
Modern EEPROM devices are “erasable” in that the memory cell transistors can be biased to remove the electrons from the floating gate, by reversing the tunneling mechanism. Some EEPROM memory devices are of the “flash” type, in that a large number (a “block”) of memory cells can be simultaneously erased in a single operation. Conventional EEPROM memories can be arranged in a “NOR” fashion, which permits individual cells in each column to be separately and individually accessed. Flash EEPROM memories are also now commonly arranged as “NAND” memory, in which the source/drain paths of a group of memory cells in a column are connected in series. NAND memories can be constructed with higher density, but require all of the cells in a group to be biased to access any one of the cells in that group.
Because of the convenience and efficiency of modern flash EEPROM memories, it is now desirable and commonplace to embed EEPROM memory within larger scale integrated circuits, such as those including modern complex microprocessors, microcontrollers, digital signal processors, and other large-scale logic circuitry. Such embedded EEPROM can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage.
According to one approach, floating-gate EEPROM cells are realized by MOS transistors having two polysilicon gate electrodes. A control gate electrode in one polysilicon level is electrically connected to decode and other circuitry in the EEPROM integrated circuit, and a floating gate in another polysilicon level is disposed between the control gate electrode and the channel region of the memory transistor. In this conventional construction, the application of a high programming voltage to the control gate capacitively couples to the floating gate, and attracts electrons from the source and drain regions of the transistor to such an extent that some tunnel to, and remain trapped on, the floating gate. FIG. 1a illustrates the electrical arrangement of conventional EEPROM memory cell 2 constructed according to this double-polysilicon construction. Memory cell 2 consists essentially of a single transistor with its drain connected to bit line BL, its source at ground, and its control gate connected to word line WL. A floating gate electrode is physically disposed between the control gate and the channel region of the transistor of memory cell 2, and is thus electrically isolated from the control gate, source, and drain of the transistor. The specific physical arrangement of the floating gate relative to the other elements of memory cell 2 can vary, depending on the particular design, as known in the art.
FIG. 1b illustrates a conventional arrangement of a non-volatile memory including array 5. Array 5 includes floating-gate EEPROM memory cells 2, arranged in rows and columns. While the number of memory cells 2 in array 5 shown in FIG. 1b is very small (sixteen cells 2, in four rows and four columns), for purposes of this description, typical conventional EEPROM arrays include many more cells. Indeed, some modern non-volatile memories include thousands of memory cells 2 on a common word line. In array 5 of FIG. 1b, each row of memory cells 2 shares a common one of word lines WL0, WL1, WL2, WL3, each driven by one word line drivers 6. Each column of memory cells 2 shares a common one of bit lines BL0, BL1, BL2, BL3, each driven by one of bit line drivers 4 and coupled to one of sense amplifiers 8.
In both read and write operations, one of word lines WL0, WL1, WL2, WL3 is selected according to a row portion of an address value, and driven active by the corresponding one of word line drivers 6. As will be described in further detail below, the voltages applied in read and write operations differ. In a write or “program” operation, one or more of bit lines BL0, BL1, BL2, BL3 is selected, according to a column portion of an address value, and is driven by its corresponding one of bit line drivers 4 with the appropriate programming voltage corresponding to the data state to be written as indicated on input data lines DATA IN (i.e., whether the cell is to be programmed or not). In a read operation, bit line drivers 4 bias one or more of bit lines BL0, BL1, BL2, BL3, and sense amplifiers 8 sense the state of one or more of bit lines BL0, BL1, BL2, BL3. The particular columns from which data are to be read can be selected, in response to a column portion of the address value, by either bit line drivers 4, sense amplifiers 8, or by circuitry downstream from sense amplifiers 8. The state of the selected memory cells 2 are output from sense amplifiers 8 on lines DATA OUT.
In conventional floating-gate EEPROMs, as mentioned above, an absence of trapped electrons is the “erased” state of the memory cell, and is evident by the (n-channel) floating-gate transistor having a low threshold voltage. This state is typically considered to be a logical “1”, as drain-to-source current is conducted in response to a read voltage applied at the control gate. The “programmed” state in which electrons are trapped on the floating gate results in the floating-gate transistor having a high threshold voltage, in which source/drain current does not conduct with a read voltage applied to the control gate; this state is typically considered to be a logical “0”.
The programming of a “0” state into memory cell 2, constructed in this double-gate manner, is typically performed by the application of a high voltage at the control gate along with a relatively strong drive (voltage and current) at the drain of the floating-gate transistor of memory cell 2, with the source of the transistor at ground. For example, in one conventional technology, a programming voltage of about 9.2 volts is applied to the control gate of memory cell 2 being programmed, in combination with a voltage of about 4.2 volts to the drain of the floating-gate transistor of memory cell 2, both voltages relative to the ground level at the source of that transistor. The physical mechanism involved in the programming operation is Fowler-Nordheim tunneling of “hot” electrons from the transistor channel region through the gate dielectric and into the floating gate electrode, to which the high control gate voltage is capacitively coupled. The high voltages and relatively high currents (e.g., on the order of 150 μA/bit) required by the programming mechanism are commonly generated by on-chip charge pump circuits. Typical programming cycle times are relatively long (e.g., on the order of microseconds), and include not only the duration of the programming pulse but also significant rise and fall times for the high voltage levels. These long programming times are in sharp contrast with the relatively fast read access cycle times (e.g., below 100 nsec), and as such various memory management techniques are used to reduce the system impact of the programming cycles.
The observed response of EEPROM cells to hot carrier programming varies from cell to cell, and from device (i.e., integrated circuit) to device. These variations in programmability are due to structural variations among the floating gate transistors, and manufacturing and processing variations from wafer to wafer. In addition, the programmability for a given EEPROM cell will vary over its operating life, primarily with the number of program/erase cycles that the cell undergoes over its life. As such, one cannot be sure of the extent that an EEPROM cell is actually programmed (i.e., the number of hot carriers that are actually trapped on the floating gate, and the effect of those trapped carriers) in response to a given set of programming pulses. Modern EEPROM memories are thus typically programmed, in system use, by way of program-and-verify cycles. Conventional program-and-verify cycles consist essentially of a program cycle, followed by a read cycle to determine whether the cell has been programmed to the desired level; if so, programming to that cell is stopped to avoid “over-programming”, especially in multi-level cell (MLC) memories in which each memory cell is programmed to any one of three or more data states. In many modern EEPROM memories, programming pulses are applied to multiple cells simultaneously, with those cells that are not to be programmed (or, in the case of a previously programmed or newly-verified cell, not to be further programmed) masked from receiving programming pulses.
Of course, the necessity of performing a verify operation after one or more programming pulses greatly lengthens the overall programming cycle time. In addition, the program-and-verify approach, especially in MLC memories, requires that the programming operation itself be broken into a number of shorter programming pulses, each followed by a verify, to provide some granularity in the eventual programmed state. In those EEPROM memories in which multiple cells in the same “page” are programmed simultaneously, circuitry must also be provided to data mask those cells that are not to receive programming pulses, whether because the cell is to remain erased or is already programmed. These inefficiencies in EEPROM design, layout, and operation reduce memory density and performance.
By way of further background, U.S. Pat. No. 5,422,842, and in Cernea et al., “A 34 Mb 3.3V Serial Flash EEPROM for Solid-State Disk Applications”, Digest of Technical Papers, 1995 IEEE International Solid-State Circuits Conference, Paper TA 7.4, pp. 126, 127, 350, describe programming of flash EEPROM cells by way of a convergent programming method based on monitoring the drain current into the cell being programmed. According to this approach, a reference current is applied to a current mirror sense amplifier, to control the programming current applied to the cell; logic coupled to the sense amplifier senses a drop in the current conducted by the cell as it becomes programmed, and disconnects the bit line from the programming voltage as a result. A similar simultaneous program-and-verify approach is described in Candelier et al., “Hot Carrier Self Convergent Programming Method for Multi-Level Flash Cell Memory”, Proceedings of the 35th Annual International Reliability Physics Symposium (IEEE, 1997), pp. 104-09.